1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and particularly to a semiconductor device having a cylindrical capacitor and a method for manufacturing the semiconductor device.
2. Description of the Related Art
Recent semiconductor devices are becoming large-scale. For example, in a dynamic random access memory (hereinafter referred to as DRAM), a large 1 GB memory is put to practical use. A DRAM memory cell includes one MOS transistor and one capacitor. The capacitor is formed on a diffusion layer of the transistor or in a region across a gate and the diffusion layer and is connected to the diffusion layer.
As semiconductor devices are becoming large-scale, the sizes of elements are reduced year by year. Accordingly, the occupied areas of capacitors are also reduced. Data in the DRAM is determined to be “1” or “0” on the basis of the quantity of electric charges accumulated in the capacitor. Thus, a capacitance more than a certain value is necessary for a stable operation of the memory. The capacitance C of a capacitor is expressed by C=εS/d, where d denotes the distance between two electrodes in the capacitor (thickness of a dielectric film), ε denotes the dielectric constant of the dielectric film, and S denotes the surface area of the electrodes (contact area between the electrodes and the dielectric film). Thus, a reduction in the thickness of the dielectric film in the capacitor, the application of a film having a high dielectric constant, and an increase in the surface area of the electrode are important to secure the capacitance of the capacitor.
In recent years, tantalum oxide (Ta2O5) and aluminum oxide (Al2O3) both having a higher dielectric constant than a nitride film (Si3N4) are used as the film having a high dielectric constant, in place of the nitride film. One of the methods for increasing the surface area of the electrode is to use hemispherical silicon grains (HSGs) to form irregularities on the surface and thereby form a rough surface. This method provides an electrode having a surface area about twice as large as that of a conventional electrode.
A method for forming the HSGs is as follows. First, an amorphous silicon layer serving as a lower electrode of a cylindrical capacitor is seeded by heat treatment in a SiH4 or Si2H6 atmosphere. Then, the amorphous silicon layer is heat-treated under high vacuum to cause silicon atoms to migrate and thereby grow a crystal grain during crystallization around the seeded Si atom nucleus.
Too many impurities, such as phosphorus (P) atoms, in the amorphous silicon inhibit the migration of silicon and thereby prevent the crystal grain from growing. Hence, the amorphous silicon is generally subjected to an HSG treatment (a treatment that forms HSGs on the surface) in the presence of about 1 to 2×1020 atom s/cm3 or less of impurities to grow the crystal grain sufficiently. When the impurities, for example, phosphorus (P) atoms are needed because of their shortage, the amorphous silicon layer may be heat-treated again in a PH3 atmosphere to introduce P atoms into the silicon layer after the HSG treatment.
As elements are reduced in size, the cylindrical capacitor must also be reduced in size. Several techniques have been disclosed to reduce the size of the cylindrical capacitor. Japanese Unexamined Patent Application Publication No. 2000-058790 discloses a technique to achieve sufficient electrical separation between adjacent cells. In this technique, ions are implanted into an amorphous silicon film to prevent HSGs from growing on the top surface of an insulating film serving as a separator between adjacent capacitors.
Japanese Unexamined Patent Application Publication No. 2000-156476 discloses a technique to grow uniform crystal grains over the entire surface of a capacitor electrode and achieve sufficient electrical conductivity. In this technique, amorphous silicon grains are formed and are subjected to an HSG treatment. Then, polycrystalline silicon is laminated on the silicon grains.
However, new problems have arisen in a cylinder hole having a higher aspect ratio in a smaller cylindrical capacitor. An etched cylinder hole having a higher aspect ratio has different opening areas at the top surface, a bowing portion, and the bottom. Specifically, the bottom of the cylinder hole has a smaller opening area. FIGS. 1A and 1B shows this situation.
As illustrated in FIG. 1A, a mask insulating film 33 and an interlayer insulating film 34 are formed on an interlayer insulating film 31 provided with a contact plug 32. Then, a capacitor hole (cylinder hole) 35 is bored to form a cylindrical capacitor. The capacitor hole 35 has an opening area defined by lithography on the uppermost surface of the interlayer insulating film 34 (hereinafter referred to as top surface), as indicated by Da in FIG. 1a. A bowing portion at a slightly lower position from the top surface has an opening area larger than that defined by the lithography, as indicated by Db. Furthermore, the opening area of the hole gradually decreases in a region lower than the bowing portion. The bottom of the hole has the minimum opening area, as indicated by Dc.
In particular, in a recent large-scale integration semiconductor device having an aspect ratio of at least 10, an etching gas flowing into the capacitor hole 35 enhances the etching of the bowing portion and thereby increases the opening area at the bowing portion. However, the concentration of the etching gas decreases with increase in the depth from the top surface. Thus, the lower portion may be etched insufficiently. As a result, the opening area of the hole decreases with increase in the depth from the top surface. The bottom of the hole has the minimum opening area. The decrease in etching rate at the bottom of the hole is known as a microloading effect. The smaller opening area at the lower region of the capacitor hole causes new problems as follows.
As illustrated in FIG. 1B, silicon is grown in the capacitor hole 35 to form a lower electrode of the capacitor and is subjected to the HSG treatment to form HSGs 36. Then, the top surface of the interlayer insulating film 34 and the HSGs 36 are covered with a capacitive dielectric film 37. Since the opening area is small in the lower region of the capacitor hole 35, the HSGs in opposite regions on the sidewall of the hole may come into contact with each other and thereby block the cylinder. Thus, a capacitor is not formed in a region lower than the blocked portion. This extremely decreases the capacitance and may cause malfunction of a semiconductor device.
Furthermore, when the HSGs formed in opposite regions on the sidewall of the hole come close to each other, a reactant gas may be supplied insufficiently. This prevents the formation of the capacitive dielectric film 37 in the regions and causes variations in the thickness of the capacitive dielectric film 37. In a region where the capacitive dielectric film 37 has a decreased thickness, accumulated charges may leak from the capacitor because of an increased leakage current or a short. This may hamper the operation of a memory and cause malfunction of a semiconductor device.
The present assignee deliberated these issues and proposed a manufacturing method described in Japanese Patent Application No. 2004-186805. According to this proposal, the blockage of a cylinder is prevented by increasing the concentration of impurities in amorphous silicon at the bottom and in a lower region of a capacitor hole by ion implantation or a diffusion method and thereby decreasing the crystal grain size of HSGs on the bottom and in the lower region of the hole.